(1) Field of Invention
The present invention relates to a static-type semiconductor memory device and more particularly to a MIS static-type semiconductor memory device in which the potentials of all the bit lines are forced to be lower than or equal to a low-level of a logic signal of the bit lines, thereby enabling a high-speed readout operation to be carried out.
(2) Description of the Prior Art
In recent years, the memory capacity of a semiconductor memory device has become very large, and, according to the increase in the memory capacity, the size of the memory cells and/or peripheral circuit elements has become very small. Therefore, the drive capacity of each memory cell and the gm (transconductance) of each of the load transistors connected between the bit lines and a power source are relatively small. Since the stray capacitance of each bit line becomes relatively large in accordance with the increase in the memory capacity, both the rise time and the fall time of a bit line potential becomes relatively long, thereby deteriorating the readout speed.
A static-type semiconductor memory device disclosed in Japanese Patent Application No. 56-13940 (corresponding to Unexamined Patent Publication No. 57-130285 (Kokai)) filed by the present applicant, where a memory device comprises a circuit for disconnecting all the memory cells from the bit lines when an address signal is changed and a circuit for rapidly precharging all the bit lines to a high-potential level. The readout speed of this static-type semiconductor memory device is greatly increased due to its structure.
However, in the memory device disclosed in the above-mentioned application, it is difficult to rapidly pull up the potentials of the bit lines because the gm of the charging transistors becomes small in accordance with the rise of the potentials of the bit lines. Moreover, since the speed of discharging the bit lines toward a low-potential level cannot be very fast, the device can be improved by further increasing the readout speed.